1. Field of the Invention
The present invention generally relates to a manufacturing method of a semiconductor device having electrode pads in plural semiconductor chip forming regions provided in a semiconductor substrate.
2. Description of the Related Art
One type of semiconductor device is a so-called chip size package (CSP) having a size substantially the same as the semiconductor chips and illustrated in FIG. 1.
FIG. 1 is a cross-sectional view of the above example of the semiconductor device.
Referring to FIG. 1, one type of semiconductor device 200 typically includes a semiconductor chip 201, a check pattern 202, an internal connection terminal 203, an insulating layer 204, a wiring pattern 205, a solder resist layer 207 and an external connection terminal 208.
The semiconductor chip 201 includes a semiconductor substrate 211, a semiconductor element 212, an electrode pad 213 and a protection film 216.
The semiconductor substrate 211 is a thin substrate and has an element forming face 211A on which the semiconductor element 212 is formed. The semiconductor substrate has a stepped portion 221 which surrounds the semiconductor element 212 and is substantially arranged on a side of the element forming face 211A.
The semiconductor element 212 is formed on the element forming face 211A. The electrode pad 213 is arranged on the semiconductor element 212. The electrode pad 213 is electrically connected to the semiconductor element 212. The electrode pad 213 has a connecting face 213A.
The protection film 216 is formed on the semiconductor element 212 and the element forming face 211A. The connecting face 213A and the checking terminal connecting face 224A are exposed to an outside through the protection film 216.
The check pattern 202 is provided for testing electrical characteristics. The check pattern 202 includes a check pattern body 223 (Test Element Group, hereinafter referred to as TEG), and a check pattern electrode 224 having a checking terminal connecting face 224A. The check pattern body 223 is formed on an outer peripheral portion of the element forming face 211A. The check pattern electrode 224 is formed on the check pattern body 223. The checking terminal connecting face 224A is a face to which a terminal (not illustrated) of inspection equipment (e.g. prove station) is connected.
The internal connection terminal 203 is formed on the connecting face 213A of the electrode pad 213. The internal connection terminal 203 has a flat connecting face 203A.
The insulating resin layer 204 is provided to cover the semiconductor chip 201, a side surface of the internal connection terminal 203, the check pattern 202 and the stepped portion 221.
By forming the stepped portion 221 and the insulating resin layer 204 covering the side surfaces of the stepped portion 221 and the semiconductor chip 201, it is possible to prevent the insulating resin layer 204 from peeling off from semiconductor substrate 211 when plural of the semiconductor devices 200 are separated into individual semiconductor devices 200 in the process illustrated in FIG. 8.
The connecting face 203A of the internal connection terminal 203 is exposed through the insulating resin layer 204. The insulating resin layer 204 has a wiring forming face 204A which is substantially planar relative to the connecting face 203A of the internal connection terminal 203.
The wiring pattern 205 is formed on the wiring forming face 204A. The wiring pattern 205 is connected to the connecting face 203A of the internal connection terminal 203. In this way, the wiring pattern 205 is electrically connected to the semiconductor chip 201 via the internal connection terminal 203. The wiring pattern 205 has a terminal connecting face 205A on which the external connection terminal 208 is formed.
The solder resist layer 207 is formed on the wiring forming face 204A. The solder resist layer 207 has an opening 207A through which the terminal connecting face 205A is exposed.
The external connection terminal 208 is formed on the terminal connecting face 205A. The external connection terminals 208 are electrically connected to pads of an implementing board (not illustrated) such as a motherboard when the semiconductor device 200 is installed in implementing the board.
FIG. 2 through FIG. 8 illustrate manufacturing processes of the semiconductor device illustrated in FIG. 1. Referring to FIG. 2 through FIG. 7, regions J are semiconductor chip forming regions (hereinafter referred to as semiconductor chip forming region J), regions K are scribing regions (hereinafter referred to as scribing region K), and regions L are cutting regions where the semiconductor substrate 231 is cut (hereinafter referred to as cutting region K).
Referring to FIG. 2 through FIG. 8, a method of manufacturing the first semiconductor device 200 illustrated in FIG. 1 is described.
Referring to FIG. 2, the semiconductor substrate 231 having plural regions for forming semiconductor chips J, plural scribing regions K surrounding the plural regions for forming the semiconductor chips J, and cutting regions L having widths narrower than the scribing regions K is prepared. The semiconductor substrate 231 is made of a mother material of the semiconductor substrate 211 illustrated in FIG. 2. At this stage, the semiconductor substrate 231 is not thinned. The scribing regions K include plural belt-like regions orthogonally crossing each other.
Then, the semiconductor chips 201 are formed on the surface 231A of the semiconductor substrate 231 in correspondence with the plural regions for forming the semiconductor chips J. The check patterns 202 are formed on the surfaces 231A of the semiconductor substrate 231 in correspondence with the scribing regions K.
Thereafter, a terminal (not illustrated) of the inspection equipment such as a prove station is made to come in contact with the checking terminal connecting face 224A for testing electrical characteristics of the check pattern 202.
Referring to FIG. 3, grooves 233 are formed by dicing in the scribing region K including plural orthogonally crossing regions for partly removing the check patterns 202. The check patterns 202 which are not removed by the dicing are left on both sides of the grooves 233.
The dicing is carried out every one line. Therefore, the grooves are formed after the dicing is carried out plural times. The width M of the groove 233 is less than the width of the scribing region K and greater than the width of the cutting region L. When the width of the scribing region K is 100 μm and the width of the cutting region L is 40 μm, the width M of the groove 233 may be 60 μm.
Referring to FIG. 4, the internal connection terminal 203 is formed on the connecting face 213A of the electrode pad 213. At this stage, the internal connection terminal 203 is shaped like a cone.
Next, referring to FIG. 5, a sheet-like insulating resin (i.e. the base material of the insulating resin layer 204) which is partially hardened is pressed toward the upper surface of the structure illustrated in FIG. 4 and the sheet-like insulating resin is completely hardened. Thus, the flat connecting face 203A is formed on the internal connection terminal 203, the grooves 233 are filled with the sheet-like insulating resin, and the insulating resin layer 204 is formed to cover the plural semiconductor chips 201.
Referring to FIG. 6, the wiring pattern 205 is formed on the wiring forming face 204A of the insulating layer 204. Thereafter, the solder resist layer 207 having an opening portion 207A and the external connection terminal 208 are sequentially formed.
Referring to FIG. 7, the semiconductor substrate 231 is thinned from a side of the surface 231B positioned opposite to the surface 231A of the semiconductor substrate 231. With this, the structures corresponding to the semiconductor devices 200 are formed in the plural regions for forming the semiconductor chips J. At this stage, the plural semiconductor devices 200 are not separated.
Referring to FIG. 8, the plural semiconductor devices 200 are obtained by cutting the structure illustrated in FIG. 7 at portions corresponding to the cutting regions L. As described, plural semiconductor devices 200 are manufactured.
However, the check patterns 202 are removed with low accuracy in the manufacturing method illustrated in FIG. 1. Said differently, the accuracy of a dicing blade relative to a cutting position of an object to be processed is generally insufficient. Therefore, it is necessary to substantially reduce the width M of the groove 233 in comparison with the width of the scribing region K.
When the check pattern 202 is removed after substantially reducing the width M of the groove 233 relative to the width of the scribing region K, the check pattern 202 which could not be removed is left on the both sides of the groove 233 (see FIG. 3).
Because the check pattern 202 is brittle, peeling or chipping of the check pattern 202 may occur which thereby drops the yield in manufacturing the semiconductor devices 200.
Because a contact of the semiconductor substrate 231 and the insulating layer 204 is weak in the manufacturing method of the semiconductor devices 200 illustrated in FIG. 1, the insulating resin layer 204 may be peeled off from the semiconductor substrate 231 or 211 when the semiconductor substrate 231 is cut in reference to FIG. 8. Therefore, the yield drops in the manufacturing method of the semiconductor devices 200.
Further, because the grooves 233 are processed by the plural times of the dicing, the manufacturing time of the semiconductor device 200 increases and, said differently, the productivity of fabricating the semiconductor devices 200 drops.
[Patent Document 1] Japanese Laid-open Patent Publication No. 2001-168231